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| INTEGRATED CIRCUITS DATA SHEET TEA1202TS 0.95 V starting power unit Preliminary specification Supersedes data of 2000 Jun 08 2002 Mar 14 Philips Semiconductors Preliminary specification 0.95 V starting power unit CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 9 10 11 12 13 13.1 13.1.1 13.1.2 13.1.3 13.1.4 13.1.5 13.1.6 13.1.7 13.1.8 13.1.9 13.1.10 13.2 13.3 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Control mechanism Synchronous rectification Start-up Undervoltage lockout Shut-down Power switches Temperature protection Current limiters External synchronization and PWM-only mode Behaviour at input voltage exceeding the specified range Low drop-out voltage regulators Low battery detector LIMITING VALUES THERMAL CHARACTERISTICS QUALITY SPECIFICATION CHARACTERISTICS APPLICATION INFORMATION External component selection Inductor L1 DC-to-DC input capacitor C1 DC-to-DC output capacitor C2 Diode D1 Feedback resistors R1 and R2 Current limiting resistor R10 Reference voltage decoupling capacitor C5 LDO output capacitors C3 and C4 LDO feedback resistors R3, R4, R5 and R6 Low battery detector components R7, R8, R9 and C6 Application recommendations Typical performance characteristics 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18 PACKAGE OUTLINE SOLDERING TEA1202TS Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS 2002 Mar 14 2 Philips Semiconductors Preliminary specification 0.95 V starting power unit 1 FEATURES 3 GENERAL DESCRIPTION TEA1202TS * Fully integrated battery power unit, including complete DC-to-DC converter circuit, two Low Drop-Out voltage regulators (LDOs) and a battery low detector * Configurable for 1, 2 or 3-cell Nickel-Cadmium (NiCd) or Nickel Metal Hybrid (NiMH) batteries and 1 Lithium Ion (Li-Ion) battery * Guaranteed DC-to-DC converter start-up from 1-cell NiCd or NiMH battery, even with a load current * Upconversion or downconversion * Internal power MOSFETs featuring a low RDSon of approximately 0.1 * Synchronous rectification for high efficiency * Soft start * PWM-only operating option * LDO drop-out voltage of 30 mV at 50 mA * Both LDOs can also be used as low-ohmic power switches * Stable LDO performance with ceramic capacitors * At start-up, LDO1 can be loaded * Stand-alone low battery detector requires no additional supply voltage * Low battery detection level at 0.90 V, externally adjustable to a higher level * Adjustable output voltages * Shut-down function * Small outline package * Advanced 0.6 m BICMOS process. 2 APPLICATIONS The TEA1202TS is a fully integrated battery power unit including a high efficiency DC-to-DC converter which runs from a single-cell NiCd or NiMH battery, two low drop-out voltage regulators and a low battery detector. The circuit can be arranged in many ways to optimize the application circuit of a power supply system. Therefore, most inputs and outputs are separated, the DC-to-DC converter can be arranged for upconversion or downconversion and the regulators can also be used as power switches. One regulator can be used completely independent of the rest of the system, and the low battery detector can be configured for several types of batteries. Accurate low battery detection is possible while all other blocks are switched off. The DC-to-DC converter features efficient, compact and dynamic power conversion using a digital control concept comparable with Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM), integrated CMOS power switches with a very low RDSon and fully synchronous rectification. The device operates at a switching frequency of 600 kHz which enables the use of external components with minimum size. The switching frequency can be synchronized to an external high frequency clock signal. Optionally, the device can be kept in PWM control mode only. Deadlock is prevented by an on-chip undervoltage lockout circuit. Active current limiting enables efficient conversion in pulsed-load systems such as Global System for Mobile communication (GSM) and Digital Enhanced Cordless Telecommunications (DECT). Both LDOs show a low drop-out voltage and are inherently stable, even when ceramic capacitors with a low ESR value are applied at the outputs. Usage of the LDOs as low-ohmic switches is also possible. LDO1 can be loaded at start-up. The low battery detector has a built-in detection level which is optimum for a single-cell NiCd or NiMH battery. Higher battery voltages can be translated to this single-cell level by an additional built-in LDO circuit. * Cellular phones * Cordless phones * Personal Digital Assistants (PDAs) * Portable audio players * Pagers * Mobile equipment. 4 ORDERING INFORMATION TYPE NUMBER TEA1202TS PACKAGE NAME SSOP20 DESCRIPTION plastic shrink small outline package; 20 leads; body width 4.4 mm VERSION SOT266-1 2002 Mar 14 3 Philips Semiconductors Preliminary specification 0.95 V starting power unit 5 QUICK REFERENCE DATA SYMBOL DC-to-DC converter UPCONVERSION VI(up) VO(up) VI(start) VO(uvlo) VI(dwn) VO(dwn) Iq(DCDC) Ishdwn ILX(max) Ilim input voltage output voltage start-up input voltage undervoltage lockout voltage IL < 10 mA note 1 VI(start) 0.93 2.0 - PARAMETER CONDITIONS MIN. TEA1202TS TYP. MAX. UNIT 5.50 5.50 1.00 2.4 V V V V VO(uvlo) - 0.96 2.2 DOWNCONVERSION input voltage output voltage VO(uvlo) - 1.30 - VLBI1 = VI(up) = 1.2 V Tamb = 80 C Ilim set to 1.0 A upconversion downconversion POWER MOSFETS RDSon(N) RDSon(P) EFFICIENCY efficiency upconversion see Fig.10; VO up to 3.3 V VI = 1.2 V; IL = 100 mA VI = 2.4 V; IL = 200 mA TIMING fsw fi(sync) tstart switching frequency synchronization clock input frequency start-up time PWM mode 480 6 - 600 13 10 720 20 - kHz MHz ms - - 84 92 - - % % drain-to-source on-state resistance drain-to-source on-state resistance NFET; IDS = 100 mA; Tj = 27 C PFET; IDS = -100 mA; Tj = 27 C - - 110 125 200 250 m m -12 -12 - - +12 +12 % % - - - 110 65 - 5.50 5.50 - - 1.0 V V A A A CURRENT LEVELS quiescent current at pin UPOUT/DNIN current in shut-down mode maximum continuous current at pins LX1 and LX2 current limit deviation 2002 Mar 14 4 Philips Semiconductors Preliminary specification 0.95 V starting power unit TEA1202TS SYMBOL PARAMETER CONDITIONS MIN. TYP. - 30 - 500 MAX. UNIT Low drop-out voltage regulators VLDO Vdropout ILDO output voltage range drop-out voltage output current VLDO < V4 + 0.3 V ILDO = 50 mA in regulation VI(LDO1) = 5 V; VFB1 < 0.4 V; ILDO1 = 50 mA 1.30 - - - 5.50 45 250 750 V mV mA m RDSon(LDO1) LDO1 drain-to-source on-state resistance General characteristics Vref Note reference voltage 1.165 1.190 1.215 V 1. The undervoltage lockout level shows wide specification limits since it decreases at increasing temperature. When the temperature increases, the minimum supply voltage of the digital control part of the IC decreases and therefore the correct operation of this function is guaranteed over the whole temperature range. The undervoltage lockout level is measured at pin UPOUT/DNIN. 2002 Mar 14 5 Philips Semiconductors Preliminary specification 0.95 V starting power unit 6 BLOCK DIAGRAM TEA1202TS handbook, full pagewidth 3 11 LBI2 12 Vref 10 LBI1 13 SHDWN2 IN2 OUT2 FB2 TEA1202TS SHDWN0 LOW BATTERY DETECTOR Vref LDO2 9 6 LBO LX1 LX2 14 1 20 sense FET ILIM 5 START-UP CIRCUIT P-type POWER FET LDO1 7 4 OUT1 FB1 UPOUT/DNIN INTERNAL SUPPLY 8 GND Vref N-type POWER FET CURRENT LIMIT COMPARATOR CONTROL LOGIC AND MODE GEARBOX 16 Vref FB0 TEMPERATURE PROTECTION sense FET 13 MHz OSCILLATOR 17 GND0 SYNC GATE 18 2 TIME COUNTER DIGITAL CONTROLLER 19 REFERENCE 15 VOLTAGE Vref MGU062 SYNC/PWM SHDWN0 U/D Fig.1 Block diagram. 2002 Mar 14 6 Philips Semiconductors Preliminary specification 0.95 V starting power unit 7 PINNING SYMBOL LX1 SHDWN0 SHDWN2 UPOUT/DNIN ILIM OUT1 FB1 GND FB2 OUT2 IN2 LBI2 LBI1 LBO Vref FB0 GND0 SYNC/PWM U/D LX2 8 8.1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION inductor connection 1 DC-to-DC shut-down input LDO2 shut-down input up mode DC-to-DC output; down mode DC-to-DC input current limiting resistor connection LDO1 output LDO1 feedback input internal supply ground LDO2 feedback input LDO2 output LDO2 input low battery detector input 2 low battery detector input 1 low battery detector output reference voltage DC-to-DC feedback input DC-to-DC converter ground synchronization clock input or PWM-only selection input conversion mode selection input inductor connection 2 handbook, halfpage TEA1202TS LX1 1 SHDWN0 2 SHDWN2 3 UPOUT/DNIN 4 ILIM 5 20 LX2 19 U/D 18 SYNC/PWM 17 GND0 16 FB0 TEA1202TS OUT1 6 FB1 7 GND 8 FB2 9 OUT2 10 MGU060 15 Vref 14 LBO 13 LBI1 12 LBI2 11 IN2 Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION Control mechanism The DC-to-DC converter of the TEA1202TS is able to operate in PFM (discontinuous conduction) or PWM (continuous conduction) operating mode. All switching actions are completely determined by a digital control circuit which uses the output voltage level as its control input. This novel digital approach enables the use of a new pulse width and frequency modulation scheme, which ensures optimum power efficiency over the complete range of operation of the converter. When high output power is requested, the device will operate in PWM (continuous conduction) operating mode. This results in minimum AC currents in the circuit components and hence optimum efficiency, minimum costs and low EMC. In this operating mode, the output voltage is allowed to vary between two predefined voltage levels. As long as the output voltage stays within this so-called window, switching continues in a fixed pattern. 2002 Mar 14 7 When the output voltage reaches one of the window borders, the digital controller immediately reacts by adjusting the pulse width and inserting a current step in such a way that the output voltage stays within the window with higher or lower current capability. This approach enables very fast reaction to load variations. Figure 3 shows the response of the converter to a sudden load increase. The upper trace shows the output voltage. The ripple on top of the DC level is a result of the current in the output capacitor, which changes in sign twice per cycle, times the internal Equivalent Series Resistance (ESR) of the capacitor. After each ramp-down of the inductor current, i.e. when the ESR effect increases the output voltage, the converter determines what to do in the next cycle. As soon as more load current is taken from the output the output voltage starts to decay. Philips Semiconductors Preliminary specification 0.95 V starting power unit TEA1202TS handbook, full pagewidth load increase Vo start corrective action high window limit low window limit time IL time MGK925 Fig.3 Response to load increase. handbook, full pagewidth maximum positive spread of VO Vwdw(high) 2% +2% Vwdw(high) VO (typ) 2% Vwdw(low) -2% Vwdw(low) upper specification limit Vwdw(high) 2% typical situation Vwdw(low) maximum negative spread of VO lower specification limit MGU576 Fig.4 Output voltage window spread. 2002 Mar 14 8 Philips Semiconductors Preliminary specification 0.95 V starting power unit When the output voltage becomes lower than the low limit of the window, a corrective action is taken by a ramp-up of the inductor current during a much longer time. As a result, the DC current level is increased and normal PWM control can continue. The output voltage (including ESR effect) is again within the predefined window. Figure 4 shows the spread of the output voltage window. The absolute value is mostly dependent on spread, while the actual window size [Vwdw(high) - Vwdw(low)] is not affected. For one specific device, the output voltage will not vary more than 2% (typical value). In low output power situations, the TEA1202TS will switch over to PFM (discontinuous conduction) operating mode. In this mode, regulation information from an earlier PWM operating mode is used. This results in optimum inductor peak current levels in the PFM mode, which are slightly larger than the inductor ripple current in the PWM mode. As a result, the transition between PFM and PWM mode is optimum under all circumstances. In the PFM mode the TEA1202TS regulates the output voltage to the high window limit as shown in Fig.3. 8.2 Synchronous rectification 8.4 Undervoltage lockout TEA1202TS As a result of too high a load or disconnection of the input power source, the output voltage can drop so low that normal regulation cannot be guaranteed. In this event, the device switches back to start-up mode. If the output voltage drops even further, switching is stopped completely. 8.5 Shut-down When the shut-down input is set HIGH, the DC-to-DC converter disables both switches and power consumption is reduced to a few microamperes. 8.6 Power switches The power switches in the IC are one N-type and one P-type power MOSFET, both having a typical drain-to-source resistance of 100 m. The maximum continuous current in the power switches is 1.0 A at Tamb = 80 C. 8.7 Temperature protection For optimum efficiency over the whole load range, synchronous rectifiers inside the TEA1202TS ensure that during the whole second switching phase, all inductor current will flow through the low-ohmic power MOSFETs. Special circuitry is included which detects when the inductor current reaches zero. Following this detection, the digital controller switches off the power MOSFET and proceeds with regulation. 8.3 Start-up When the DC-to-DC converter operates in the PWM mode, and the die temperature gets too high (typical value is 160 C), the converter and both LDOs stop operating. They resume operation when the die temperature falls below 90 C again. As a result, low frequency cycling between the on and off state will occur. It should be noted that in the event of device temperatures at the cut-off limit, the application differs strongly from maximum specifications. 8.8 Current limiters Start-up from low input voltage in the boost mode is realized by an independent start-up oscillator, which starts switching the N-type power MOSFET as soon as the low-battery detector detects a sufficiently high voltage. The inductor current is limited internally to ensure soft-starting. The switch actions of the start-up oscillator will increase the output voltage. As soon as the output voltage is high enough for normal regulation, the digital control system takes control over the power MOSFETs. If the current in one of the power switches exceeds the programmed limit in the PWM mode, the current ramp is stopped immediately and the next switching phase is entered. Current limiting is required to keep power conversion efficient during temporary high loads. Furthermore, current limiting protects the IC against overload conditions, inductor saturation, etc. The current limiting level is set by an external resistor which must be connected between pin ILIM and ground for downconversion, or between pins ILIM and UPOUT/DNIN for upconversion. 2002 Mar 14 9 Philips Semiconductors Preliminary specification 0.95 V starting power unit 8.9 External synchronization and PWM-only mode TEA1202TS Both LDOs are protected from high temperature (see Section 8.7). Next to normal LDO functions, both regulators can be switched off or can be used as switches. Each regulator will act as a low-ohmic switch in the on-state when its feedback input is connected to ground. When the feedback input is higher than 2 V, the regulator will make its power FET high-ohmic. So the feedback inputs of the regulators can be used as digital inputs which make the LDOs behave as switches. 8.12 Low battery detector If an external high-frequency clock or a HIGH level is applied to pin SYNC/PWM, the TEA1202TS will use PWM regulation independent of the load applied. In the event a high-frequency clock is applied, the switching frequency in the PWM mode will be exactly that frequency divided by 22. In the PWM mode the quiescent current of the device increases. In the event that no external synchronization or PWM mode selection is necessary, pin SYNC/PWM must be connected to ground. 8.10 Behaviour at input voltage exceeding the specified range The low battery detector is an autonomous circuit which can work at an input voltage down to 0.90 V. It is always on, even when all other blocks are in the shut-down mode. The detector has two inputs: the input on pin LBI1 is tuned to accept a single-cell NiCd or NiMH battery voltage directly, while the input on pin LBI2 can detect a two-cell NiCd or NiMH battery voltage or higher voltage. The detection level of the input on pin LBI2 can be set by using a voltage divider between the battery voltage, pin LBI2 and ground. Hysteresis is included for proper operating. Furthermore, a capacitor of 10 nF (typical value) must be connected between pin LBI1 and ground when the input on pin LBI2 is used. The output of the low battery detector on pin LBO is an open-collector output. The output is high (i.e. no current is sunk by the collector) when the input voltage of the detector is below the lower detection level. In general, an input voltage exceeding the specified range is not recommended since instability may occur. There are two exceptions: * Upconversion: at an input voltage higher than the target output voltage, but up to 5.5 V, the converter will stop switching and the external Schottky diode will take over. The output voltage will equal the input voltage minus the diode voltage drop. Since all current flows through the external diode in this situation, the current limiting function is not active. In the PWM mode, the P-type power MOSFET is always on when the input voltage exceeds the target output voltage. The internal synchronous rectifier ensures that the inductor current does not fall below zero. As a result, the achieved efficiency is higher in this situation than standard PWM-controlled converters achieve. * Downconversion: when the input voltage is lower than the target output voltage, but higher than 2.2 V, the P-type power MOSFET will stay conducting resulting in an output voltage being equal to the input voltage minus some resistive voltage drop. The current limiting function remains active. 8.11 Low drop-out voltage regulators The low drop-out voltage regulators are functionally equal apart from the shut-down mechanism: LDO2 can be controlled separately by pin SHDWN2, while LDO1 is controlled by pin SHDWN0 like the DC-to-DC converter. The input voltage of each LDO must be 250 mV (at ILDO = 50 mA) higher than its output voltage to achieve full specification on e.g. ripple rejection. However, the parts will function like an LDO down to a margin of 45 mV (at ILDO = 50 mA) between input and output: the so-called drop-out voltage. At a lower margin between input and output, the LDOs will behave like a resistor. 2002 Mar 14 10 Philips Semiconductors Preliminary specification 0.95 V starting power unit 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL Vn Tj Tamb Tstg Ves Notes 1. ESD specification is in accordance with the JEDEC standard: PARAMETER voltage on any pin junction temperature ambient temperature storage temperature electrostatic handling voltage notes 1 and 2 CONDITIONS shut-down mode operating mode MIN. -0.2 -0.2 -40 -20 -40 TEA1202TS MAX. +6.5 +5.5 +150 +80 +125 V V UNIT C C C V Class II a) Human Body Model (HBM) tests are carried out by discharging a 100 pF capacitor through a 1.5 k series resistor. b) Machine Model (MM) tests are carried out by discharging a 200 pF capacitor via a 0.75 H series inductor. 2. Exception is pin ILIM: 1000 V HBM. 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS VALUE 140 UNIT K/W thermal resistance from junction to ambient in free air 11 QUALITY SPECIFICATION In accordance with "SNW-FQ-611D". 12 CHARACTERISTICS Tamb = -20 to +80 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified. SYMBOL DC-to-DC converter UPCONVERSION; pin U/D = LOW VI(up) VO(up) VI(start) VO(uvlo) VI(dwn) VO(dwn) REGULATION VO(wdw) output voltage window size as a PWM mode function of output voltage 1.5 2.0 2.5 % input voltage output voltage start-up input voltage undervoltage lockout voltage IL < 10 mA note 1 VI(start) VO(uvlo) 0.93 2.0 - - 0.96 2.2 - - 5.50 5.50 1.00 2.4 V V V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DOWNCONVERSION; pin U/D = HIGH input voltage output voltage note 2 VO(uvlo) 1.30 5.50 5.50 V V 2002 Mar 14 11 Philips Semiconductors Preliminary specification 0.95 V starting power unit TEA1202TS SYMBOL CURRENT LEVELS Iq(DCDC) Ishdwn Ilim(max) Ilim PARAMETER CONDITIONS - - - Ilim set to 1.0 A; note 4 upconversion downconversion MIN. TYP. - - - MAX. UNIT A A A % % A quiescent current at pin UPOUT/DNIN current in shut-down mode maximum current limit current limit deviation note 3 VLBI1 = VI(up) = 1.2 V 110 65 5 - - - -12 -12 - +12 +12 1.0 ILX(max) maximum continuous current at pins LX1 and LX2 Tamb = 80 C POWER MOSFETS RDS(on)(N) RDS(on)(P) EFFICIENCY efficiency upconversion see Fig.10; VO up to 3.3 V VI = 1.2 V; IL = 100 mA VI = 2.4 V; IL = 200 mA TIMING fsw fi(sync) tstart VlL(n) VIH(n) switching frequency synchronization clock input frequency start-up time note 6 PWM mode 480 6 - 0 note 7 0.55V4 0.9 - - V4 + 0.3 V V4 + 0.3 V V4 + 0.3 V 5.50 5.50 45 135 - - V V mV mV mV mV 600 13 10 - 720 20 - 0.4 kHz MHz ms - - 84 92 - - % % drain-to-source on-state resistance drain-to-source on-state resistance NFET; IDS = 100 mA; Tj = 27 C PFET; IDS = -100 mA; Tj = 27 C - - 110 125 200 250 m m DIGITAL INPUT LEVELS LOW-level input voltage on all digital pins HIGH-level input voltage pin SYNC/PWM pins SHDWN0 and SHDWN2 all other digital input pins Low drop-out voltage regulators; note 8 VI(LDO1) VI(LDO2) VLDO Vdropout output voltage range pin LDO1 output voltage range pin LDO2 output voltage range drop-out voltage VLDO < V4 + 0.3 V note 9 ILDO = 50 mA ILDO = 150 mA Vdrop minimum drop voltage for ILDO = 50 mA functionality within specification ILDO = 150 mA - - 250 500 30 90 - - VO(uvlo) 1.8 1.30 - - - V4 + 0.3 V V V4 - 0.4 - 2002 Mar 14 12 Philips Semiconductors Preliminary specification 0.95 V starting power unit TEA1202TS SYMBOL ILDO VLDO Vline PARAMETER output current output voltage accuracy line voltage regulation CONDITIONS in regulation VI - VLDO = 1 V; ILDO = 1 mA; note 10 1 mA < ILDO < 150 mA; note 11 (VI - VLDO) > Vdrop < 4.5 V - 4.5 V < (VI - VLDO) < 5.5 V - - MIN. - - -3.5 TYP. MAX. 250 +3.5 UNIT mA % - - - 40 - 0.1 0.2 -0.02 - 20 %/V %/V %/mA dB s Vload PSRR tres(up) load voltage regulation with changing load current power supply ripple rejection response time after a positive load step 10 mA < ILDO < 150 mA; note 12 note 13 IO = 0.5 mA to 50 mA; CL = 2.2 F; VO(error) < 0.1% of end value IO = 50 mA to 0.5 mA; CL = 2.2 F; VO(error) < 0.1% of end value - - - tres(down) response time after a negative load step - - 100 s Iq(LDO) Ishdwn(LDO) quiescent current shut-down current - - LD01 in switched-on state; Vl(LDO1) = 5 V; VFB1 < 0.4 V LD02 in switched-on state; Vl(LDO2) = 5 V; VFB2 < 0.4 V LDO1 in switched-on state; VFB1 > 0.4 V LDO2 in switched-on state; VFB2 > 0.4 V falling Vbat falling Vbat - - - - 50 - 500 300 - - - 1 A A m m A A SWITCH CIRCUIT RDS(on)(LD01) LD01 drain-to-source resistance RDS(on)(LD02) LD02 drain-to-source resistance IO(max)(LDO1) IO(max)(LDO2) LDO1 maximum output current LDO2 maximum output current 750 450 0.40 0.40 Low battery detector tt(HL) Vdet Vhys TCVdet TCVhys transition time - 0.87 - - - 2 - 0.93 - - - s V mV mV/K mV/K DETECTION INPUT PIN LBI1 low battery detection level low battery detection hysteresis temperature coefficient of detection level temperature coefficient of detection hysteresis 0.90 20 0 0.175 DETECTION OUTPUT PIN LB0 IO(sink) output sink current 15 - - A 2002 Mar 14 13 Philips Semiconductors Preliminary specification 0.95 V starting power unit TEA1202TS SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT General characteristics Vref Iq Tamb Tmax Notes 1. The undervoltage lockout level shows wide specification limits since it decreases at increasing temperature. When the temperature increases, the minimum supply voltage of the digital control part of the IC decreases and therefore the correct operation of this function is guaranteed over the whole temperature range. The undervoltage lockout level is measured at pin UPOUT/DNIN. 2. When VI(dwn) is lower than the target output voltage but higher than 2.2 V, the P-type power MOSFET will remain conducting (duty factor is 100%), resulting in VO(dwn) following VI(dwn). 3. The quiescent current is specified as the current in to pin UPOUT/DNIN (pin 4) in the upconversion configuration at VI = 1.20 V and VO = 3.30 V, using L1 = 6.8 H, R1 = 150 k and R2 = 91 k. 4. The current limit is defined by resistor R10. This resistor must have 1% accuracy. 5. The specified efficiency is valid when using an output capacitor having an ESR of 0.1 and an inductor of 6.8 H with an ESR of 0.05 and a sufficient saturation current level. 6. The specified start-up time is the time between the connection of a 1.20 V input voltage source and the moment the output reaches 3.30 V. The output capacitance equals 100 F, the inductance equals 6.8 H and no load is present. 7. V4 is the voltage at pin UPOUT/DNIN. If the applied HIGH-level voltage is less than V4 - 1 V, the quiescent current of the device will increase. 8. Take care regarding total dissipation if output current ILDO > 50 mA and drop voltage Vdrop > 2 V. 9. The drop-out voltage is defined as the voltage between the input and the output of the LDO when the output voltage has dropped 100 mV below its nominal value. The drop-out voltage is measured while the LDO input voltage is decreasing. 10. The output voltage of each LDO is defined by external feedback resistors. These resistors must have 1% accuracy. V LDO 11. V line = ---------------------------- x 100 %/V. V LDO x V I V LDO 12. V load = --------------------------------- x 100 %/mA. V LDO x I LDO 13. Measured with a sine wave at fi = 100 Hz to 1 MHz, Vi = 100 mV (RMS), CL = 2.2 F and ILDO = 10 mA. reference voltage quiescent current at pin UPOUT/DNIN ambient temperature internal temperature for cut-off all blocks operating 1.165 - -20 150 1.190 270 +25 160 1.215 - +80 170 V A C C 2002 Mar 14 14 Philips Semiconductors Preliminary specification 0.95 V starting power unit 13 APPLICATION INFORMATION TEA1202TS handbook, full pagewidth DC/DC UPCONVERTER LDO1 DC/DC output regulator 1 output regulator 2 output low battery detection TEA1202TS LDO2 LOW BATTERY DETECTOR equivalent block diagram D1 L1 LX1 1 LX2 C1 IN2 20 11 16 LBI1 R7 low battery detection LBI2 LBO U/D 13 12 14 19 7 OUT1 R3 FB1 R4 C3 regulator 1 output 5 4 ILIM R10 DC/DC output UPOUT/DNIN R1 FB0 R2 C2 6 TEA1202TS external clock DC/DC shut-down regulator 2 shut-down SYNC/PWM SHDWN0 SHDWN2 Vref C5 18 2 3 15 8 GND 9 10 OUT2 R5 FB2 C4 regulator 2 output 17 R6 GND0 MGU063 Fig.5 Application in single-cell NiCd or NiMH battery powered equipment. 2002 Mar 14 15 Philips Semiconductors Preliminary specification 0.95 V starting power unit TEA1202TS handbook, full pagewidth DC/DC UPCONVERTER LDO1 DC/DC output regulator 1 output regulator 2 output low battery detection TEA1202TS LDO2 LOW BATTERY DETECTOR equivalent block diagram D1 L1 LX1 LX2 C1 IN2 LBI1 R8 C6 R2 LBI2 R7 R9 U/D 12 19 6 OUT1 R3 7 FB1 R4 external clock DC/DC shut-down regulator 2 shut-down SYNC/PWM SHDWN0 SHDWN2 Vref C5 18 2 3 15 8 GND 9 FB2 10 OUT2 R5 C4 regulator 2 output C3 regulator 1 output 1 20 11 13 16 FB0 5 4 ILIM R10 DC/DC output UPOUT/DNIN R1 C2 TEA1202TS low battery detection LBO 14 17 R6 GND0 MGU064 Fig.6 Application in two-cell NiCd or NiMH battery powered equipment. 2002 Mar 14 16 Philips Semiconductors Preliminary specification 0.95 V starting power unit TEA1202TS handbook, full pagewidth control regulator 1 switch DC/DC output SWITCH LDO1 LDO2 LOW BATTERY DETECTOR output regulator 1 switch regulator 2 output low battery detection DC/DC UPCONVERTER TEA1202TS equivalent block diagram D1 L1 LX1 LX2 C1 IN2 LBI1 R8 C6 R2 LBI2 R7 R9 U/D 12 1 20 11 13 16 FB0 5 4 ILIM R10 DC/DC output UPOUT/DNIN R1 C2 TEA1202TS 19 6 OUT1 output regulator 1 switch control regulator 1 switch low battery detection external clock LBO 14 7 FB1 SYNC/PWM SHDWN0 SHDWN2 Vref C5 18 2 3 15 8 GND 9 FB2 10 OUT2 R5 C4 regulator 2 output 17 R6 GND0 MGU065 Fig.7 Application in two-cell NiCd or NiMH battery powered equipment with autonomous shut-down at low battery voltage and using LDO1 as a switch. 2002 Mar 14 17 Philips Semiconductors Preliminary specification 0.95 V starting power unit TEA1202TS handbook, full pagewidth DC/DC output DC/DC DOWNCONVERTER LDO1 regulator 1 output regulator 2 output low battery detection TEA1202TS LDO2 LOW BATTERY DETECTOR equivalent block diagram 5 UPOUT/DNIN 4 20 1 ILIM LX2 LX1 R10 IN2 11 C1 C6 R8 LBI2 R7 R9 LBI1 13 L1 D1 R1 C2 R2 DC/DC output 16 FB0 12 OUT1 R3 7 FB1 R4 18 2 3 15 8 GND 9 FB2 R6 OUT2 R5 C4 regulator 2 output C3 regulator 1 output U/D 19 6 TEA1202TS low battery detection external clock DC/DC shut-down regulator 2 shut-down LBO 14 SYNC/PWM SHDWN0 SHDWN2 Vref C5 10 17 GND0 MGU066 Fig.8 Application in three-cell NiCd or NiMH and single-cell Li-Ion battery powered equipment. 2002 Mar 14 18 Philips Semiconductors Preliminary specification 0.95 V starting power unit TEA1202TS handbook, full pagewidth USB supply 5V BAW62 0.95 to 1.5 V 1 20 Vbat 120 F 16 68 k LDO1 6 120 k 7 68 k 3.3 V load 2.2 F DC/DC CONVERTER 4 130 k 120 F TEA1202TS MGU589 Fig.9 Application with USB and single-cell NiCd or NiMH battery supply. 13.1 External component selection 13.1.4 DIODE D1 Component references apply to the circuits shown in Figs 5 to 8. 13.1.1 INDUCTOR L1 The performance of the TEA1202TS is not very sensitive to inductance value. The best efficiency performance over a wide load current range is achieved by using an inductance of 6.8 H, for example TDK SLF7032 or Coilcraft DO1608 range. 13.1.2 DC-TO-DC INPUT CAPACITOR C1 The Schottky diode is only used for a short time during takeover from N-type power MOSFET and P-type power MOSFET and vice versa. Therefore, a medium-power diode is sufficient in most applications, for example Philips PRLL5819. 13.1.5 FEEDBACK RESISTORS R1 AND R2 The output voltage of the DC-to-DC converter is determined by the resistors R1 and R2. The following conditions apply: * Only use 1% tolerance SMD-type resistors. If larger body-size resistors are used, the capacitance on pin FB0 will be too large and could cause inaccurate operation * Resistors R1 and R2 should have a maximum value of 50 k when connected in parallel. A higher value will result in inaccurate operation. Under these conditions the output voltage can be calculated by the formula: R1 V O = V ref x 1 + ------- R2 The value of C1 depends strongly on the type of input source. In general, a 100 F tantalum capacitor is sufficient. 13.1.3 DC-TO-DC OUTPUT CAPACITOR C2 The value and type of C2 depends on the maximum output current and the ripple voltage which is allowed in the application. Low-ESR tantalum capacitors show good results. The most important specification of C2 is its ESR, which mainly determines output voltage ripple. 2002 Mar 14 19 Philips Semiconductors Preliminary specification 0.95 V starting power unit 13.1.6 CURRENT LIMITING RESISTOR R10 TEA1202TS 13.1.10 LOW BATTERY DETECTOR COMPONENTS R7, R8, R9 AND C6 Resistor R7 is connected between pin LBO and the input or output pin and must be 330 k or higher. A single-cell NiCd or NiMH battery can be connected directly to pin LBI1. A higher battery voltage must be applied to pin LBI2 using a divider circuit with resistor R8 and R9. In that situation, capacitor C6 (10 nF) must be connected between pin LBI1 and ground. The low-battery detection level for a higher battery voltage can be set by the resistors at pin LBI2 using the formula: R8 V LBI2 = 0.90 x 1 + ------- R9 13.2 Application recommendations The maximum instantaneous current is set by the external resistor R10. The preferred type is SMD, 1% accuracy. The connection of resistor R10 differs for each mode: * At upconversion: resistor R10 must be connected between pins ILIM and UPOUT/DNIN; the current 320 limiting level is defined by: I Iim = ---------R10 * At downconversion: resistor R10 must be connected between pins ILIM and GND0; the current limiting level 300 is defined by: I Iim = ---------R10 The average inductor current during limited current operation also depends on the inductance value, input voltage, output voltage and resistive losses in all components in the power path. Ensure that Ilim < Isat (saturation current) of the inductor. 13.1.7 REFERENCE VOLTAGE DECOUPLING CAPACITOR C5 1. Connect loads above approximately 30 mA via LDO1 to avoid start-up problems. 2. Apply minimum input voltage to minimize the power dissipation of the LDOs. 3. For optimum LDO performance, the required drop voltage is 250 mV at ILDO = 50 mA and 500 mV at ILDO = 150 mA; the minimum required voltage drop is calculated by Iload x 900 m. 4. Minimum LDO input capacitance is 2.2 F. 5. Minimum LDO output capacitance is 2.2 F for load currents between 0 and 150 mA and 4.7 F for load currents between 0 and 250 mA. 6. X7R or X5R-type ceramic capacitors with a minimum ESR of 10 m must be used on the LDO outputs. 7. With the USB and battery powered concept shown in Fig.9, LDO1 is used as a regulator and not as a switch. For a good load regulation, the DC-to-DC converter is set at 3.5 V and the LDO at 3.3 V. This reduces the efficiency by approximately 5%. However, the efficiency can be improved by lowering the voltage drop, but this will reduce the output voltage performance. 8. In two or more cell applications, pin LBI1 is not used and should be decoupled with a 10 nF capacitor. 9. In a single-cell application pin LBI2 is not used and should be connected to ground. 10. The maximum continuous current at pins LX1 and LX2 is 1 A. During experiments, especially at low input voltages, the current can rise excessively. Avoid this situation by using a power supply with a 1 A current limit. 20 Optionally, a decoupling capacitor can be connected between pin Vref and ground in order to achieve a lower noise level of the output voltages of the LDO. The best choice for C5 is a ceramic multilayer capacitor of approximately 10 nF. 13.1.8 LDO OUTPUT CAPACITORS C3 AND C4 A typical LDO output capacitor is a ceramic multilayer capacitor of 2.2 F, for example GRM40X5R225K6.3 from Murata. The ESR of the output capacitor must be at least 10 m to achieve stability and the specified transient response. 13.1.9 LDO FEEDBACK RESISTORS R3, R4, R5 AND R6 The output voltage of each LDO can be set by the external feedback resistors. Their values can be derived from the formulae: R3 V O = V ref x 1 + ------- R4 VO R5 = V ref x 1 + ------- R6 The maximum value for each of the LDO feedback resistors is 500 k. 2002 Mar 14 Philips Semiconductors Preliminary specification 0.95 V starting power unit 13.3 Typical performance characteristics TEA1202TS handbook, full pagewidth 100 MGU577 (%) (1) (2) 80 60 40 1 10 10 2 IL (mA) 10 3 (1) VI = 2.4 V. (2) VI = 1.2 V. VO = 3.5 V Fig.10 Efficiency as a function of load current. 2002 Mar 14 21 Philips Semiconductors Preliminary specification 0.95 V starting power unit TEA1202TS handbook, full pagewidth 2.50 MGU579 VI(start) (V) 2.00 (1) 1.50 1.00 (2) (3) 0.50 0.00 0 50 100 150 IL (mA) 200 (1) Two-cell start-up. (2) Single-cell start-up. (3) Minimum supply voltage after start-up. VI = 2.4 V; VO = 3.5 V. Fig.11 Start-up voltage and minimum supply voltage as a function of load current. handbook, full pagewidth 600 MGU578 RDS(on) m 500 LDO1 400 300 LDO2 200 100 0 0.00 1.00 2.00 3.00 4.00 5.00 VI (V) 6.00 Fig.12 LDO1 and LDO2 drain-to-source on-state resistance as a function of input voltage. 2002 Mar 14 22 Philips Semiconductors Preliminary specification 0.95 V starting power unit 14 PACKAGE OUTLINE SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm TEA1202TS SOT266-1 D E A X c y HE vM A Z 20 11 Q A2 pin 1 index A1 (A 3) Lp L A 1 e bp 10 detail X wM 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.20 0.13 D (1) 6.6 6.4 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 10 0o o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT266-1 REFERENCES IEC JEDEC MO-152 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-22 99-12-27 2002 Mar 14 23 Philips Semiconductors Preliminary specification 0.95 V starting power unit 15 SOLDERING 15.1 Introduction to soldering surface mount packages TEA1202TS If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 15.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 15.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2002 Mar 14 24 Philips Semiconductors Preliminary specification 0.95 V starting power unit 15.5 Suitability of surface mount IC packages for wave and reflow soldering methods TEA1202TS SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable 2002 Mar 14 25 Philips Semiconductors Preliminary specification 0.95 V starting power unit 16 DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS TEA1202TS This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Preliminary data Qualification Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 17 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2002 Mar 14 26 Philips Semiconductors Preliminary specification 0.95 V starting power unit NOTES TEA1202TS 2002 Mar 14 27 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2002 SCA74 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 403502/02/pp28 Date of release: 2002 Mar 14 Document order number: 9397 750 09361 |
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